1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device, and particularly to a semiconductor integrated circuit device provided with an internal potential generating circuit, which allows external tuning of an internal power supply potential.
2. Description of the Background Art
A conventional semiconductor integrated circuit device is provided with an internal power supply potential generating circuit for producing an internal power supply potential, which is lower or higher than an external power supply potential, and applying it to internal circuits. Since the output potential of the internal power supply potential generating circuit varies due to variations in manufacturing process and others, the device is generally configured to allow external tuning of the output potential of the internal power supply potential generating circuit.
In the prior art, however, the output potential of the internal power supply potential generating circuit is tuned while monitoring it by an external tester. Therefore, the tuning is not easy.
In recent years, a system LSI or the like may be provided with internal power supply potential generating circuits for supplying different internal power supply potentials to internal circuits having different functions, respectively. In this structure, it is necessary to tune the output potential levels of the plurality of internal power supply potential generating circuits while monitoring these output potential levels by a tester. This increases the difficulty in tuning.
Results of such tuning of the internal power supply generating circuit must be finally stored in a nonvolatile manner within the semiconductor integrated circuit device. Processing for such storage will be referred to as xe2x80x9cprogramming processingxe2x80x9d hereinafter.
Such programming is generally performed by blowing fuse elements in the prior art. However, for programming an output potential level of each of a plurality of internal power supply potential generating circuits, many fuse elements are required, which is disadvantageous from the viewpoint of a circuit area.
Accordingly, it is desired that the element for programming the output potential level allows nonvolatile programming of data.
Attention is being given to a MRAM (Magnetic Random Access Memory) device as a memory device, which can nonvolatilely store data with low power consumption. The MRAM device is a memory device, in which a plurality of thin film magnetic elements are formed in a semiconductor integrated circuit for nonvolatilely storing data, and random access to each thin film magnetic element is allowed.
Particularly, in recent years, it has been announced that a performance of the MRAM device can be dramatically improved by using the thin film magnetic elements, which utilize the MTJs (magnetic tunnel junctions), as memory cells. The MRAM device with memory cells having the magnetic tunnel junctions has been disclosed in technical references such as xe2x80x9cA 10 ns Read and Write Non-Volatile Memory Array Using a Magnetic Tunnel Junction and FET Switch in each Cellxe2x80x9d, ISSCC Digest of Technical Papers, TA7.2, Feb. 8, 2000, and xe2x80x9cNonvolatile RAM based on Magnetic Tunnel Junction Elementsxe2x80x9d, ISSCC Digest of Technical Papers, TA7.3, Feb. 8, 2000.
FIG. 32 conceptually shows a structure of a memory cell, which has a magnetic tunnel junction, and may be merely referred to as an xe2x80x9cMTJ memory cellxe2x80x9d hereinafter.
Referring to FIG. 32, a MTJ memory cell includes a tunneling magneto-resistance element TMR having an electric resistance, which is variable in accordance with a level of storage data, and an access transistor ATR for forming a path of a sense current Is passing through tunneling magneto-resistance element TMR in a data read operation. Access transistor ATR is formed of, e.g., a field-effect transistor, and is coupled between tunneling magneto-resistance element TMR and a fixed voltage (ground voltage Vss).
For the MTJ memory cell, the structure includes a write word line WWL for instructing data writing, a read word line RWL for executing data reading and a bit line BL, which is a data line for transmitting an electric signal in accordance with the data level of the storage data.
FIG. 33 conceptually shows an operation of reading data from the MTJ memory cell.
Referring to FIG. 33, tunneling magneto-resistance element TMR has a ferromagnetic layer, which has a uniform magnetization direction, and may be merely referred to as a xe2x80x9cfixed magnetic layerxe2x80x9d hereinafter, and a ferromagnetic layer VL, which is magnetized in a direction depending on an externally applied magnetic field, and may be merely referred to as a xe2x80x9cfree magnetic layerxe2x80x9d hereinafter. A tunneling barrier TB formed of an insulator film is disposed between fixed magnetic layer FL and free magnetic layer VL. Free magnetic layer VL is magnetized in the same direction as fixed magnetic layer FL or in the different direction in accordance with the data level of the storage data.
In the data read operation, access transistor ATR is turned on in response to activation of read word line RWL. Thereby, sense current Is can flow through a current path formed of bit line BL, tunneling magneto-resistance element TMR, access transistor ATR and ground voltage Vss.
Tunneling magneto-resistance element TMR has an electric resistance, which is variable depending on a correlation in magnetization direction between fixed magnetic layer FL and free magnetic layer VL. More specifically, when the magnetization direction of fixed magnetic layer FL and the magnetization direction written in free magnetic layer VL are uniform (parallel) direction, the electric resistance of tunneling magneto-resistance element TMR is smaller than that in the case where these layers FL and VL are magnetized in the opposite directions, respectively.
As described above, the tunneling magneto-resistance element TMR has the electric resistance, which is variable depending on the magnetization direction. Therefore, data storing can be performed by determining a relationship between the two magnetization directions of free magnetic layer VL in tunneling magneto-resistance element TMR and the levels (xe2x80x9c1xe2x80x9d and xe2x80x9c0xe2x80x9d) of the stored data.
Changes in voltage, which are caused in tunneling magneto-resistance element TMR by sense current Is, depend on the magnetization direction of the free magnetic layer, i.e., the storage data level. For example, if sense current Is is passed through tunneling magneto-resistance element TMR after precharging bit line BL to a predetermined voltage, the storage data of the MTJ memory cell can be read out by detecting the voltage on bit line BL.
FIG. 34 conceptually shows an operation of writing data in the MTJ memory cell.
Referring to FIG. 34, read word line RWL is inactive, and access transistor ATR is off in the data write operation. In this state, the data write currents for magnetizing free magnetic layer VL in the direction depending on the level of the write data are supplied to write word line WWL and bit line BL, respectively. The magnetization direction of free magnetic layer VL depends on the respective data write currents flowing through write word line WWL and bit line BL.
FIG. 35 conceptually shows a relationship between the direction of the data write current and the magnetization direction in the data write operation.
Referring to FIG. 35, an abscissa Hx gives a direction of a data write magnetic field H (BL) produced by the data write current flowing through bit line BL. An ordinate Hy indicates a direction of a data write magnetic field H(WWL) produced by the data write current flowing through write word line WWL.
The magnetization direction of free magnetic layer VL can be rewritten only when a sum of applied magnetic fields H(BL) and H(WWL) falls within a region outside an asteroid characteristic line shown in FIG. 35.
Therefore, the magnetization direction of free magnetic layer VL does not change when the data write magnetic fields applied thereto have intensities corresponding to a region inside the asteroid characteristic line. For updating the storage data of the MTJ memory cell, currents at a predetermined level or higher must be passed through both write word line WWL and bit line BL, respectively. The magnetization direction, which was once written into tunneling magneto-resistance element TMR, and thus the storage data of MTJ memory cell is held nonvolatilely until next data writing is executed.
In the data read operation, sense current Is flows through bit line BL. However, the sense current Is is generally determined to be smaller by one or two digits than the data write current already described. Therefore, such a possibility is small that sense current Is affects to rewrite erroneously the storage data of the MTJ memory cell in the data read operation.
The references described before have disclosed technologies for integrating such MTJ memory cells on a semiconductor substrate to provide a random access memory MRAM device.
However, a sufficient study has not been conducted on appropriate circuit structures for performing the foregoing xe2x80x9cprogramming processingxe2x80x9d with such xe2x80x9ctunneling magneto-resistance element TMRsxe2x80x9d, and there is a problem that the circuit structure required for the xe2x80x9cprogramming processingxe2x80x9d is not sufficiently clarified.
An object of the invention is to provide a semiconductor integrated circuit device, which allows easy tuning of internal power supply potentials produced by a plurality of internal power supply generating circuits.
Another object of the invention is to provide a semiconductor integrated circuit device, which can electrically and nonvolatilely record results of tuning of internal power supply potentials produced by a plurality of internal power supply generating circuits.
In summary, the invention provides a semiconductor integrated circuit device including at least one internal circuit, an internal potential generating circuit, a test control circuit, a measuring circuit and a transmitting circuit.
The internal circuit performs predetermined processing based on at least data applied externally with respect to the semiconductor integrated circuit device or data transmitted mutually. The internal potential generating circuit is provided corresponding to the internal circuit for receiving a level set signal including information representing a level of an internal potential, and producing an internal potential at a level corresponding to the level set signal. The internal potential generating circuit includes a comparing circuit for comparing a comparison reference potential with a level corresponding to the level set signal in a test operation. The test control circuit controls test processing of a level of an output potential of the internal potential generating circuit, and operates in the test operation to apply successively the plurality of level set signals to the internal potential generating circuit. The measuring circuit performs measurement in the test operation for detecting a set value required in the level set signal based on results of the comparison by the comparing circuit between the levels corresponding to the plurality of level set signals and the comparison reference potential. The transmitting circuit transmits results of the measurement of the measuring circuit to the test control circuit.
According to another aspect of the invention the semiconductor integrated circuit device includes a program circuit for holding information relating to the semiconductor intergrated circuit device. The program circuit includes a latch circuit for receiving a power supply potential via first and second power supply nodes. The latch circuit is activated in response to power-on of the latch circuit. The program circuit further includes first and second tunneling magneto-resistance elements arranged between the first and second power supply nodes and the latch circuit, respectively.
According to another aspect of the invention, a semiconductor integrated circuit device includes at least one internal circuit, an internal potential generating circuit, a test control circuit, a measuring circuit and a transmitting circuit.
The internal circuit performs predetermined processing based on at least data applied externally with respect to the semiconductor integrated circuit device or data transmitted mutually. The internal potential generating circuit is provided corresponding to the internal circuit for receiving a level set signal including information representing a level of an internal potential, and producing an internal potential at a level corresponding to the level set signal.
The internal potential generating circuit includes a comparing circuit and a potential control circuit. The comparing circuit operates in a normal operation to compare the internal potential generated by the internal potential generating circuit with the level corresponding to the level set signal, and operates in a test operation to stop the comparison between the level corresponding to the level set signal and the internal potential, and to compare a comparison reference potential with the level corresponding to the level set signal. The potential control circuit tunes the level of the internal potential in accordance with an output of the comparing circuit.
The test control circuit controls test processing of a level of the output potential of the internal potential generating circuit, and operates in the test operation to apply successively the plurality of level set signals to the internal potential generating circuit for successively generating the plurality of internal potentials at different levels, respectively. The measuring circuit performs measurement in the test operation for detecting a set value required in the level set signal based on results of the comparison by the comparing circuit between the respective internal potentials generated by the internal potential generating circuit and the comparison reference potential. The transmitting circuit transmits results of the measurement of the measuring circuit to the test control circuit.
Accordingly, the invention has the following advantage. In the structure having the internal potential generating circuits corresponding to the internal circuits, respectively, the level set signal for producing the internal potential corresponding to the reference potential can be easily detected based on the output signal of the measuring circuit. Therefore, the internal potential can be easily tuned based on results of the detection. Further, it is possible to reduce a time required for detecting processing of this level set signal.
Further, the invention has such an advantage that the value of the detected level set signal can be programmed with a magneto-resistance element.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.